FPGA implementation and verification of efficient and reconfigurable CNN-LSTM accelerator design
Hongmin He, Danfeng Qiu, Fen Ge · 2023
Verilog language is used to complete the RTL modeling of the high efficiency LSTM accelerator and the reconfigurable CNN-LSTM accelerator on FPGA. Through comparing the calculation results of hardware and software, the functional correctness of the designed accelerator is confirmed. The experimental results show that the proposed high efficiency LSTM accelerator has 16 times the acceleration ratio of the CPU, 19.12% of the power consumption of the GPU, 85.68 GOPS of throughput, and 22.4 GOPS/W of energy efficiency, which is superior to other LSTM accelerator designs of the same type. Compared with the CPU, the proposed reconfigurable CNN-LSTM accelerator can achieve 12 times the acceleration ratio, while the power consumption is only approximately 10.02% of GPU; the throughput rate reaches 77.5 GOPS, and the energy efficiency ratio is 42.9 GOPS/W. In the same application background, compared with the efficient LSTM accelerator, on-chip resource consumption is reduced while decreasing the time consumed to process a set of data by 65%.