Towards Survivable In-Memory Stores with Parity Coded NVRAM
Z. Y. Wang, Guangping Xu, Hongzhang Yang, Yulei Wu · 2023
Erasure codes have been widely applied to in-memory key-value storage systems for high reliability and low redundancy. In distributed in-memory key-value storage systems, update operations are relatively frequent, especially the partial-stripe update, which makes data update more challenging. Recently, existing research has been based on appending logs to accelerate parity data write. However, its logs are stored on disks, which decreases the system performance significantly. Therefore, we propose a novel in-memory key-value storage architecture, DNVPL, which utilizes NVRAM to log parity data. Our main idea is to design an appending-only update scheme to tradeoff the memory cost and the update overhead. We implement DNVPL with an in-memory key-value storage prototype, called LogKV. We evaluate it with different workloads. The experiments show that our scheme achieves high update performance from different metrics. Our scheme can reduce update latency by up to 49% and save storage space by 48% compared to the state-of-the-art schemes.