Implementation of FIFO design using Verilog HDL to avoid data losses in transmission
R. Seetharaman, P. S. Harsha Ruban, S. Arumai Shiney, L. Harihara Subramanian, M. Ganeshakumar, R. Adityaa, S. Gayathri · 2024
DFSR (Direct Feedback Shift Register) counters incorporate a network router switch through which the bundle enters. The parcel is then driven out through three result ports, each containing three sections: header, information, and edge, crucial for examining the arrangement. The parcel has a width of 8 pieces, and its length can range from 1 byte to 63 bytes. The objective address (DA) of the parcel is 8 pieces, guiding the change to individual ports based on the destination address. Each result port is assigned an 8-digit unique port location. If the parcel's exact address matches the port location, the change directs the bundle to the respective result port, with the data length being 8 pieces.