Semi-Custom Design of Fast Multiplier Based on Vedic Sutras
Nanotechnology Perceptions · 2024
A multiplier is a crucial component of general-purpose processors and digital signal processors, which are frequently employed in tasks like image processing, communication systems, and digital signal processing, among others.Multipliers are necessary for fundamental signal processing tasks like convolution, Fast Fourier Transform, digital filtering, etc.As a result, there is a growing need for optimised high-speed, low-power multipliers.Most VLSI implementations make use of multiplier architectures such as the Wallace Tree multiplier, Array Multiplier, Booth Multiplier, Bot Serial Multiplier, Carry Save Multiplier, and Modified Booth Multiplier.This essay primarily focuses on the application of Vedic mathematics to develop a high-speed multiplier with a very compact footprint.The broad Vedic mathematics sutra is Urdhva-Tiryagbhyam, one of the sixteen.The present study involves the creation of a 16-bit fixed point multiplier utilising the Urdhva-Tiryagbhyam (vertically and across) sutra.The implementation of the multiplier is carried out on the Spartran6 FPGA, utilising the Verilog HDL description.The design is functionally verified using ISim Simulator and synthesised using the Xilinx ISE 14.2 tool.The 16-bit multiplier, designed utilising Vedic sutra, demonstrates exceptional performance in terms of speed, memory utilisation, and area utilisation.