Systems and Debugging Supports for Hardware Designs
Jiacheng Ma · Deep Blue (University of Michigan) · 2024
The development and deployment of hardware and software have traditionally been quite distinct. Software benefits from an agile development cycle, aided by a wide array of debugging tools---such as step-wise debuggers, logging frameworks, and both static and dynamic analyses---and is further simplified by its integration with multiple layers of systems---such as hypervisors, operating systems, and libraries. Unfortunately, such debugging and systems supports are less explored and usually not available in the hardware domain. This dissertation envisions that by integrating software-like systems and debugging supports into the hardware domain, the development and deployment of hardware can be markedly improved, thereby aligning them more closely with software practices. Accordingly, this dissertation conducts preliminary explorations in designing and developing such supports tailored for different hardware designs including those based on Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). Specifically, it presents three studies and systems that demonstrate the feasibility and benefits of these supports. First, this dissertation introduces Optimus, the first hypervisor designed for shared-memory FPGA platforms. Optimus incorporates both spatial and temporal multiplexing, enabling a cloud FPGA to be shared among different virtual machines in various manners. This sharing can be achieved either by partitioning the FPGA's area or by allocating specific time slots for its use, thus facilitating versatile and efficient resource utilization in a cloud environment. Moreover, Optimus scales linearly and can enhance the aggregated performance of applications running in different virtual machines until the memory bandwidth of the FPGA platform reaches its limit. Second, this dissertation conducts initial investigations into the debugging supports for FPGA-based hardware designs. It includes a comprehensive study of bugs commonly encountered in such platforms, and offers a testbed of 20 hardware bugs that can be easily reproduced in a push-bottom manner. Based on this study and the testbed, the dissertation also proposes a suite of specialized debugging tools designed to assist in the localization of these bugs. The final part of this dissertation addresses the challenge of aging-related silent data corruptions (SDCs) that are increasingly observed in data centers. It introduces Vega, a bottom-up approach that constructs concise and effective tests for the detection of aging-related SDCs by examining the hardware's implementation details. To construct such tests, Vega identifies aging-prone signal propagation paths using a model for transistor aging, and then lifts these paths into software-executable test cases using a combination of formal methods and heuristics. Finally, Vega integrates the generated tests into applications, therefore allowing aging-related SDCs to be efficiently and effectively identified at application runtime.