A Hardware Accelerator for Sparse Computing Based on NVDLA
Yizhou Chen, De Ma, Jiada Mao · 2024
This paper introduces a hardware acceleration architecture based on sparsity and implements it on the foundation of NVDLA. This optimization accelerates computation and reduces dynamic power consumption by actively skipping zero elements in the convolution. The design adopts a sparse compressing method, CSB, and a load balancing algorithm. The design is implemented on the XILINX ZYNQ 7045 FPGA platform, with an operating frequency set at 100MHz. The result achieves a 1.79x acceleration, with power consumption reduced to 91.36% of its pre-optimization value at the cost of only 9.5% increase in area.