Hardware Efficient FIR Filter for Signal Processing Applications
Pa Saisivakumaran, S Surendhar, V Saai Miruthunjayan, Karuthapandian Mariammal · 2024
This work produced a power and area efficient architecture of FIR filter where the existing VLSI signal processing algorithms were utilized. The algorithms included in the reference paper [1] was a novel matrix CSE technique and CSD representation of filter coefficients. These techniques were used in reducing the no of nonzero terms present in filter coefficients. Seismic signal data set were converted into signal, plotted in time domain and fed into the implemented FIR filter, and conventional fourth order FIR filter. It was found that conventional filter could not process the non-periodic signal as that of implemented FIR filter. The On chip power for the implemented FIR architecture was reduced by 12.5% and the Worst Hold Slack was reduced by 13.4%. Further the number of adders used were reduced by reworking the existing fourth order FIR filter of the base paper (taken as reference). This was considered as fine improvement in the implementation as the seismic signal processing is done in real time.