FPGA Implementation of Elliptic-Curve Point Multiplication Over GF(2233) Using Booth Polynomial Multiplier for Area-Sensitive Applications
Amer Aljaedi, Furqan Aziz Qureshi, Mohammad Mazyad Hazzazi, Malik Imran, Zaid Bassfar, Sajjad Shaukat Jamal · IEEE Access · 2024
This article presents an area-efficient hardware architecture for the implementation of elliptic-curve point multiplication (PM) operation overGF(2233). The area is minimized through three strategies: (i) implementing a bit-serial-based Booth polynomial multiplication architecture to multiply two polynomials with clock cycles overhead, (ii) using one modular adder, Booth multiplier and square block in the arithmetic unit, and (iii) realizing the modular inversion computation using the implemented square and Booth multiplier circuits. Moreover, the critical path is evaluated by the placement of registers in the datapath of the PM and Booth multiplier architectures. Moreover, a dedicated finite-state machine is implemented for control functionalities. Finally, a figure-of-merit (FoM), defined as throughput/area, facilitates realistic comparisons. The implementation results are reported on Xilinx field-programmable gate array (FPGA) devices. On the Virtex-7 device, our accelerator utilizes 1343 slices and can operate on a maximum of 393MHz, requiring 174457 clock cycles and 443.91μsfor one PM computation. It consumes 1361mWpower. The implementation results and comparison to state-of-the-art show that the proposed accelerator is suitable for cryptographic applications that demand lower hardware resource utilization without significant concerns regarding computation time.