SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida · 2024
SLMLET is a low-power System-on-a-Chip (SoC), which is a promising device for edge computing. It consists of a RISC-V core and area-saving embedded Field-programmable gate arrays (eFPGA) blocks called Scalable Logic Module (SLM). This paper presents a fabricated SLMLET chip and a developed HW/SW co-design flow. The experimental results demonstrate that the RISC-V core can operate at up to 300MHz, and a hardware design on the SLM blocks can operate at up to 100MHz. By offloading compute-intensive processes to dedicated circuits implemented in the SLM blocks, it is possible to achieve up to 77 % energy reduction compared to software processing on the RISC-V core and other commercial microcontrollers.