Efficient Address-Embedded Time-Domain Implementation of Minima Finders for Soft Error-Correction Decoders
Yang Ge, Dmitri V. Truhachev, Abolfazl Zokaei, Xiaotong Lu, Xiaoting Huang, Kamal El‐Sankary · IEEE Transactions on Circuits & Systems II Express Briefs · 2024
This brief presents a novel algorithm that identifies the first six smallest values and their positions in a vector of 256 quantized positive real numbers. The proposed technique is designed for efficient time domain implementation. It operates with signals that are specially structured to contain a pulse width representation of a real number and a pulse-code of its address. The signals are passed through a tree structure where the number of stages and the comparison blocks are devised to yield the best overall performance. To demonstrate the hardware efficiency of this technique, it was successfully implemented using TSMC 65-nm CMOS technology. Experimental results unequivocally showcase that the proposed “minima finder” (MF) algorithm outperforms state-of-the-art solutions in terms of latency and complexity. This makes the proposed architecture a compelling candidate for the hardware implementation of the next-generation high-throughput forward error-correction (FEC) decoders in the realm of fiber-optical communications.