Comparative Analysis of Graph Isomorphism and Graph Neural Networks for Analog Hierarchy Labeling
Zhengfeng Wu, Ioannis Savidis · 2024
Automated synthesis of analog ICs requires recognition of circuit hierarchies at both the device level and system level. The capability of a model to distinguish between circuit structures allows for the automated synthesis of a topology given a set of specifications. The device groupings also provide symmetry and matching constraints for layout optimization. Traditional methods based on graph isomorphism matching require a manual setup of a library of primitives. While learning-based approaches have been proposed that do not require a library, the categorical specification of a detected group is not returned by prior algorithms. In addition, device sizes are utilized as features, which render the models technology-dependent and infeasible for use before device sizing is performed. To address such limitations, a relational GraphSAGE (R-SAGE) model is proposed that performs multi-class link prediction instead of binary prediction for the labeling of analog functional pairs. The R-SAGE model is characterized and compared with the subgraph isomorphism algorithm VF2 on a dataset that consists of 14 analog circuits with a total of 219 transistors and 120 functional pairs that span seven primitive categories. The R-SAGE model achieves an average macro F1-score of 0.864 and exhibits an average testing time of 80.3 ms across 10 executed runs, outperforming VF2 that provides an average F1-score of 0.841 and an average test time of 594 ms. The proposed R-SAGE model advances machine learning based reasoning of circuit topology. The learned hierarchies provide utility for downstream tasks in the modeling and design of analog circuits.