FPGA Implementation of a High-Performance SM2 Coprocessor
Tuanjie Kong · 2023
To enhance the performance of cryptographic servers, this study proposes a high-performance hardware implementation focusing on the scalar multiplication operation of the SM2 algorithm. Through a thorough analysis of the SM2 algorithm, we employed the Karatsuba-Ofman algorithm to design the multiplier, targeting time-consuming multiplication operations to reduce computational load and decrease latency. The implementation of fast modular reduction further improved the speed of modular reduction operations. For the scalar multiplication operation, we adopted the hardware implementation of the Width-w Non-Adjacent Form scalar multiplication algorithm to meet the requirements of resisting SPA attacks and reducing computational load. Experimental results demonstrate that the speed of scalar multiplication can reach 0.256ms per operation, achieving a favorable balance between resource consumption and performance.