Optimized Design of Reversible Adder andMultiplier Using Peres Gates
Premanand K. Kadbe, Shriram D. Markande · Research Square · 2024
Abstract This paper details the approach to the designand optimization of reversible adder and multiplierutilizing Peres gates which is a three input, three outputgate. Peres gates are recognized for their universality andenergy efficient properties and present an intriguingoption for constructing reversible circuits. Reversiblelogic characterized by its ability to uniquely determineinput states from output states is harnessed to create acircuit suitable for applications in quantum computing andother emerging technologies. The design methodologyinvolves a cascading arrangement of Peres gates eachperforming a reversible XOR operation on correspondingbits of the input numbers and the carry out from thepreceding stage. The paper presents a detailed schematicrepresentation, simulation results and analysis of theproposed designs showcasing their potential forreversible and quantum computing applications. Theintegration of Peres gates in the adder and multiplierdesign signifies a step forward in the exploration ofreversible logic circuits and their applications incontemporary computing paradigms.