Low Power VLSI Implementation of 32-Point FFT.
Kuruva Naresh, Doni Sanjay Kumar Yadav · International Journal of Research Publication and Reviews · 2024
This project focuses on the design and implementation of a low-power Very Large-Scale Integration (VLSI) architecture for computing the 32-point Fast Fourier Transform (FFT).The objective is to optimize power consumption while maintaining performance efficiency.Various techniques including algorithmic optimization, parallel processing, and hardware design strategies are employed to achieve this goal.The project aims to contribute to the advancement of energyefficient signal processing systems, with potential applications in areas such as wireless communication, multimedia processing, and biomedical signal analysis.