A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process
Ralph Gerard B. Sangalang, Weizhen Chen, Chua‐Chin Wang · 2023
This investigation presents a low-power content addressable memory (CAM) design using 10T single-ended cells. It uses the single-ended SRAM cell as a memory unit and a single-ended comparison circuit. By adopting this circuit, the proposed CAM cell is the first to have both the read/write and search operation to be in a single-ended mode. An energy reduction by power gating unused column is also presented in this investigation. The proposed CAM is implemented using the typical TSMC 40-nm CMOS logic process. It has an area of 1.4 × 1.4 mm2 with a core of 0.89 mm2. Simulation results show that the energy per bit per search is 0.938 fJ with a search time of 0.47 ns. An FOM comparison based on the search time, energy per bit per search, and supply voltage also showed that the proposed CAM is the best compared to prior designs.