An Efficient ALU Architecture Design for Low Power IoT Application
Yash Ijarwal, Shambhavi Tiwari, Saurav Kumar, Soumalyadeb Banerjee, Rajendra Prasad, Anuja Kumar Acharya, Srinibasa Padhy · 2024
This research proposed an efficient logic design for an Internet of Things(IoT) centric processor architecture.As it is evident that Arithmetic Logic Unit(ALU) is the prominent block in almost all processes and the control panel is used in the IoT board. The proposed ALU architecture uses a combination of clock gates and gray coding technique called CGGC, this minimizes the switching and specific selection of different operations using the architecture level optimization method.The current design was conceived using verilog code in the Vivado 16 simulation platform. The modified architecture exhibits improved performance in terms of reduced LUTs of 18% leading to low power consumption and optimized resource utilization which is solicited in IoT application.