An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA
Sakari Lahti, Tuomas Aaltonen, Elizaveta Rastorgueva-Foi, Jukka Talvitie, Bo Tan, Timo D. Hämäläinen · 2024
High-level synthesis (HLS) promises to increase the design and verification productivity for digital hardware systems. However, the industry still predominantly uses more time-consuming manual register-transfer level techniques instead of HLS. To accelerate the adoption of HLS, it is vital to explore if it is possible to achieve competitive results with this method. To that end, this paper demonstrates an HLS implementation of the well-known MUSIC algorithm for estimating the direction of arrival of a radio signal. We use as a receiver a four-antenna uniform linear array with one signal source and a resolution of one degree. For the computationally heavy eigenvalue decomposition within MUSIC, we employ the iterative Jacobi algorithm. We target two different Virtex FPGAs for synthesis and obtain results faring well in comparison to the previous literature, with$5.0\ \mu \mathrm{s}$microseconds latency, high accuracy, and low resource consumption. The results show that HLS is suitable for implementing these kinds of algorithms on FPGA.