Communication Latency Optimization Through Hardware-Direct Design in Modular Development
Kota Ushiwaka, Yoshiki YAMAGUCHI, Qin Yuanjiao, Kai Sheng · 2023
Ensuring safety, reliability, and comfort is paramount in deploying autonomous driving technologies. An integrated system of information and communication technologies supports these objectives. While advances in modular development have facilitated functional verification and enhanced the extensibility and reusability of design assets, a significant challenge remains the reduction of communication latency caused by module arbitration. Latency is a critical performance metric for real-time systems, and failure to meet specified latency requirements can compromise the viability of these systems. This article presents an empirical study on the latency incurred through hardware-direct operations in a communication framework based on conventional network standards. Utilizing a Field-Programmable Gate Array (FPGA) design, we incorporated image processing and data compression algorithms, executing all operations through hardware-direct computation. Our experimental results indicate latencies of approximately 230 µs in wired environments and 4,340 µs in wireless settings. Given that the internal computational delay within the FPGA was less than 100 µs, our findings substantiate the efficacy of employing FPGA in modular development for latency-sensitive applications.