Research on the impact of Gem5-based cache capacity on cache performance
Ruqing Wang, Lixin Yu, Wei Zhuang · 2023
Cache is a key component of the processor, how to set the cache capacity at all levels to make it more effective for performance improvement? We have conducted research on this problem by evaluating different cache sizes configurations of a dual core two-level cache architecture with GEM5 simulator and SPLASH-2 standard parallel benchmark. The experiments are divided into two aspects: (1) Keeping the sizes of icache and dcache the same, increasing L1 cache from 16KB to 64KB, and increasing the L2 cache from 512KB to 2MB respectively resulted in the decrease in the corresponding cache miss rate, with an average reduction in program runtime of 5.5% and 2.5%, respectively. This indicates that the increase in L1 cache has a significant performance improvement. (2) While keeping the L2 size at 512KB, modify the L1 icache and dcache sizes separately. Both icache and dcache were 16KB originally. When icache increases to 32KB, the program runtime decreases by 2.8%; For the same rate of decrease, dcache needs to increase to 128KB. So when designing cache structure, we can first focus on the miss rate of L1 cache. If there is still room for improvement, we can prioritize optimize L1 icache to improve performance.