SRIL: Securing Registers from Information Leakage at Register Transfer Level
Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa · 2024
The scan chain is used for the design for test (DFT) technique for testability improvement in sequential circuits. On the other hand, the scan chain of a design can be used as a side channel to retrieve the secret keys of a cryptographic implementation on hardware. This work proposes a method for protecting the registers from information leakage based on high-level synthesis (HLS) against such scan-based side-channel attacks. First, we perform a taint analysis on the behavioral specification to identify the variables that may potentially leak sensitive information like cryptographic keys explicitly or implicitly. We then identify the registers that store those leaky variables during HLS. We propose a register transfer level (RTL) bubble-pushing algorithm to break the direct correlation between the cryptographic keys and the register content to protect these registers from information leakage through scan access. To the best of our knowledge, this is the first work that proposes bubble-pushing logic at RTL and utilizes it to protect information leakage at the higher abstraction level. The experimental results on various benchmarks show that the proposed locking scheme has a negligible performance overhead.