A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit
Kripi Gupta, Ravindra Kumar Tiwari, Nikita Singh, Aachman Agrawal, Abhay Pratap Singh, R. K. Baghel · 2024
This proposed study shows a novel 1-bit fast and low-power 17-T XOR-XNOR Full adder circuit, a significant step forward in the field of digital circuit design. The XOR-XNOR circuit, which has been recognized as a vital component, has a significant impact on power consumption, driving capability, and latency—all essential aspects that directly influence the overall performance of the hybrid full adder. The proposed circuit is thoroughly tested using advanced modeling tools inside Cadence Virtuoso and advancing 45-nm CMOS technology. This analysis goes beyond the isolated circuit and explores its use in creating a functional design for arithmetic logic units (ALUs), which are essential parts of digital processors. This circuit's novel strength is in its ability to not only significantly reduce power consumption for digital processors but also to simultaneously eliminate latency, resulting in an optimal power-delay product.