A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures
Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Heng Sha, Zunxian Fu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Pengliang Kong, Yunfeng Zhao, Yaoqiang Wang, Weize Yu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2024
In this brief, a high-speed secret merchant-4 (SM4) cryptographic circuit with strong robustness against differential power analysis (DPA) attacks is proposed for securing the wireless networks for the first time. To achieve a high-throughput design for the SM4 algorithm, 32-stage pipelined encryption rounds and key expansion rounds are employed. Moreover, to resist DPA attacks, one pseudorandom number generator (PRNG) is embedded to randomly alter the SM4 circuit with a 32-stage or 34-stage pipeline, the other PRNG is utilized for realizing redundant operations to further break the correlation between the processed data and power dissipation of the SM4 circuit. When compared to a regular SM4 cryptographic circuit, the proposed SM4 architecture is capable of achieving a high throughput and satisfactory robustness against DPA attacks without compromising much power, area, and performance overhead. The result shows that the pipelined SM4 cryptographic circuit achieves a 128-Gbps throughput and 47 423-$\mu$m$^2$area with a high measurement-to-disclosure (MTD) value ($>$1 million) after synthesizing in the SMIC 14-nm process design kits (PDKs).