Upgraded Design of 4-bit Absolute-Value Detector Adopting Simplified Circuit Scheme
Kenan Xiao · 2023
In the whole arithmetic integrated digital circuit design, 4-bit absolute-value detector act as an indispensable part throughout the period. Conventionally, the research usually implements the circuit based on the requirement and logic expressions. However, it is also necessary to evaluate the designed circuit with two obvious standards: delay and power consumption. In that case, a specific assessment includes logic effort calculation and gate sizing approach should be taken into serious account to balance these two factors and figure out the optimal way of the circuit design. This paper provides a normal way to judge the related parameters and design, and figure out a relative efficient way to implement the 4-bit absolute value detector (AVD). With the help of the above description, the energy can be largely reduced within just 1.5 times of shortest delay. In that case, a better combination of the design can be worked out, resulting in a more powerful way to the design, and to the whole integrated circuit system.