Architecture Level Design of Sub-Word Multipliers for Variable-Sized and Variable-Signed Operands
Hoda Ghabeli · 2024
Variable Latency Speculative (VLS) computing is a method based on arithmetic approximation that allows early completion similar to prediction. The VLS circuit can be designed to predict a short path with reduced computations compared to the critical path. Any incorrect speculation can be corrected by an error detection and correction circuit. This technique can be generalized to applications that support variable operand sizes. This paper presents the VLS multiplier based on sub-word multipliers and includes a dynamic-range detection unit. The dynamic-range detection unit allows for switching between short and critical path based on the operand’s size and sign. The dynamic-range detection circuit operates concurrently with the sub-word multiplier to decrease the total delay. Experimental results show that applying the VLS multiplier leads to a reduction in delay with only marginal overhead in area and power consumption.