Hardware Security of Embedded Processors against Fault Injection Attacks
Noura Ait Manssour · HAL (Le Centre pour la Communication Scientifique Directe) · 2023
Embedded processors can be subject to physical attacks due to some proximity between an attacker and the circuit. Fault injection attacks (FIAs) exploit perturbations in the circuit to reveal secret data or bypass security features. Various protection methods exist against FIA: error code correction/detection, functional property check, redundancy, randomization, etc. In software, instruction duplication and triplication are easy to use to secure critical codes but lead to important overheads in execution time and code size. More, software protections rarely take into account hardware implementation details, such as the processor pipeline, and may not be as effective as intended. We propose a hardware support for instructions replay in a basic RISC processor. It consists in a small extension of the instruction set (one new instruction), a few detection and vote elements (mainly registers and comparators) and light modifications of the processor control. We explore various configurations of internal protection elements for hardware replay. The core area overhead is about +30% while the clock frequency is reduced by less than 10% on FPGA. The hardware replay allows to significantly reduce the execution time and code size compared to a pure software replay protection.