Performance Enhancement of “ARP Block” using 28nm Technology node
Vishal Mahida, Bhavesh Soni, Nilesh Ranpura · 2023
ASICs, or Application Specific Integrated Circuits, are integrated circuits that have been built for a specific usage or application, as the name implies. By decreasing the size of electrical goods and increasing the density of logic gates per chip, ASIC contributed to transform technology. Moore's law states that technology is progressing at a breakneck pace. With the progress of cutting-edge technologies into the deep submicron zone, the performance of integrated circuits is being tested by the aggravation of process variability. To meet timing limitations, physical design engineers employ several EDA tools including as ICC, ICC2, Innovus, PrimeTime, Fusion compiler, and others to optimize power, area, timing, and congestion. Timing optimization solutions must be addressed throughout certain stages of Physical design flow. In this paper, back-end design (PnR) is performed on modules called ARP Block using 28nm technology node. The entire chip is divided into clusters, and each cluster is partitioned into several blocks. ARP Block is the name of the block. We will use several timing optimization tactics to try to improve the overall worst negative slack (Setup Violation) of the timing path group REG2REG at floor-plan stage and placement stage (PNR stages) by implementing 28nm technology in the ICC tool. Nevertheless, relative to the literature survey, we decreased the time violation by 43 percent.