Asynchronous Circuit Design in Chisel Using Phase-Decoupled Click Elements
Kasper Hesse, Tjark Petersen, Jens Sparsø · 2023
This paper explores using the hardware construction language Chisel to describe, implement, and test asynchronous circuits. The Chisel language supports clocked registers and the use of multiple clocks. It is hence capable of describing asynchronous designs that are built from clocked flip-flops and logic, such as circuits using the asynchronous (phase-decoupled) click-element template that we target in this paper. Previous work has used VHDL to describe a library of asynchronous data-flow components as well as an example circuit demonstrating the use of the components. In this paper, we re-implement this work using Chisel and compare against VHDL. As we see, Chisel offers more efficient and elegant support for describing asynchronous handshake channels and for connecting components. Compared to the VHDL version, the code is reduced by up to 80 %. The example circuit computes the greatest common divisor of two integers, and it is synthesized and tested on an FPGA board. All code is open source giving those interested easy access to asynchronous design and prototyping.