An Area and Power Efficient Design of Fused integer-floating point unit for RISC-V cores
Winlog Feng, Huangxu Chen, Guozheng Lin, Xiaoyong He · 2023
With the development of intelligent algorithms and the advent of the Internet of Things era, the floating-point arithmetic unit has increasingly become an indispensable part of general-purpose processors. However, implementing additional float point unit(FPU) implies the need for a larger chip area and increased power consumption. To address the trade-off between performance, power consumption, and area in traditional floating-point arithmetic units, we propose Fused-IFPU, a structure that integrates integer and floating-point operations and supports RV32IMF. Firstly, by separating the control logic while sharing the arithmetic resources, the circuit area is significantly reduced while maintaining high computational performance. Secondly, a rational state partitioning of complex arithmetic algorithms has been employed, reducing the resource requirements and keeping the timing delays within an acceptable range. Lastly, a unified structure is adopted for floating-point division and square root operations to minimize area consumption. Synthesis report indicates that this design incurs slightly increase in timing delay but achieves a 35.81% reduction in area and a 13.97% decrease in power consumption. The benchmark results after porting it to the Hummingbird E203 platform demonstrate that the Fused-IFPU can significantly reduce area and power consumption with nearly uncompromised computational performance.