HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration
Nuocheng Wang · International Journal of Engineering and Technology · 2024
This paper introduces the logic control flow of Field-Programmable Gate Array (FPGA). The process from analyzing a digital circuit description to component mapping on FPGA is described thoroughly. This transforming process is partitioned into three major stages: combinational logic synthesis, sequential logic inference, and technology mapping. Specific algorithms are discussed for each stage.