ISSCC 2024 Session 15 Overview: Embedded Memories & Ising Computing
2024
In Paper 15.1, Tsinghua University presents a 0.795fJ/b physically-unclonable-function-protected TCAM for softwaredefined networking switching.1:55 PM 15.2A 2048×60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia Daeyeon Kim, Intel, Hillsboro, OR In Paper 15.2, Intel presents a 2048×60m4 SRAM design in Intel 4 using PowerVia.To limit the area increase of an SRAM bitcell array, while utilizing the benefits of PowerVias in logic peripherals circuits, an around-the-array powerdelivery scheme is introduced.The measured test chip demonstrates an improved or comparable V MIN and performance compared to similar non-PowerVia designs.An 8.3Mb HCC with a 2048×60m4 instance shows a clean voltage-frequency Shmoo.2:20 PM 15.3A 3nm FinFET 4.3GHz 21.1Mb/mm 2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture