Design of high-speed vedic multiplier using three-operand parallel prefix adder
Kiran Kumar Mandrumaka, Raghu Vamshider Reddy Gankidi, Manju Bhargavi, Amrita Sajja · AIP conference proceedings · 2024
Multipliers being one of the basic units of processor has a great impact on the speed of processor.Improving the speed of multipliers plays a key role in improving the efficiency of processors.Recent high-speed multiplier designed using Kogge Stone adder.Vedic multiplier is constructed using adders, and it is implemented using a variety of adder models.Due of its minimal latency, the Kogge Stone adder offers fast speed multiplication.While adding partial products, to reduce the number of stages in the multiplier.A new method is introduced for increasing the speed of multiplier by using three operand parallel prefix adder. ARCHITECTURE OF VEDIC MULTIPLIERThe Vedic multiplication approach may be applied to both decimal and binary values.This section explains the Vedic multiplication approach for binary numbers and its implementation in the 2 X 2, 4 X 4, 8 X 8, and 16X16 Vedic multiplier architectures.The development of the 2 X 2 Vedic multiplier block is critical in the implementation of the 4 X 4, 8 X 8, and 16X16 Vedic multiplier architectures. 2X2 Bits Vedic MultiplierConsider double binary digits, P and Q, each with two bits, where P is represented by p1p0 and Q by q1q0, as illustrated in Figure 1.To begin, the "p0" and "q0" bits are multiplied to get the last bit of the final result.The