A Productive HLS Simulation Approach for Multi-FPGA Systems
Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Uenoy, Kentaro Sanoy · 2024
When implementing an application on an FPGA cluster with multiple FPGAs connected, the existing high-level synthesis design environment assumes functional simulation with a single module, and it requires a great deal of effort by the designer to create verification code for processes that reproduce communication among multiple modules. Therefore, we propose a method to easily simulate the function of multi-FPGA systems by executing each process of multiple FPGAs in parallel as a task through a system-of-tasks feature.