A 100Gbps-ready Low Latency on-Chip Router for FPGA clusters
Yuiki Tani, Yasunori Osana · 2024
Several research institutes and companies have developed FPGA clusters as one of the methods for accelerating large-scale computations. The clusters consist of multiple FPGAs connected to remove the FPGAs’ circuit area limitation. This paper describes the extended router architecture of OpenFC, an open and portable toolkit for FPGA clusters. The router prioritizes low latency and low circuit area occupancy and supports 100 Gbps and higher, such as PCIe Gen4 and 100GbE. The router’s port width has been extended from 64 bits to 512 bits to meet this requirement, and the data frame header structure has been designed to accommodate the extended port width. The router can operate with any number of ports and has been confirmed with 16 ports at a 250 MHz frequency on Virtex Ultrascale + FPGAs. The circuit size of the router is about 3 % FPGA utilization for an 8-port router.