Implémentation à haute performance de la fonction de hachage cryptographique SHA3 sur des circuits FPGA
Soufiane ELMOUMNI · HAL (Le Centre pour la Communication Scientifique Directe) · 2020
The cryptographic hash function is an essential element of sensitive communications, especially in banking, military and healthcare fields. It ensures secure communication through data integrity and authenticity verification, password management,electronic signature, and other important cryptographic roles.According to the National Institute of Standards and Technology (NIST), the Keccak hash function (i.e. SHA3) is the most resistant against recent attacks due to the combination of five sub-functions (Theta, Rho, Pi, Chi and Iota) forming the core of the SHA3 algorithm. However, hardware implementation is necessary to strengthen the security of embedded systems using the SHA3, and to accelerate data processing time.In order to meet this need, our work consists in proposing two hardware implementation architectures on FPGA circuits allowing an increase in terms of maximum frequency and throughput.In our first contribution, we have reduced the critical path of data processing by using a technique that allows both multiplexing of round constants (RC) used in Iota sub- function step and reducing the number of logical operations used in Rho sub-function step.Our second contribution is revolved around increasing the throughput, and generating several output lengths of SHA3 (224, 256, 384, and 512 bits). Therefore, we have developed a hardware architecture based on parallel data processing allowing a higher throughput, and a generator block producing four output lengths.The implementation of the proposed designs was done on Xilinx FPGA devices of Virtex family (Virtex5 and Virtex6). We have used the Xilinx ISE development environment to evaluate the performances of our designs.The comparative study of related works’ results with ours shows the effectiveness of our approaches, especially in terms of maximum frequency and throughput.