Calcul hétérogène agile: le calcul hétérogène à plate-forme variable et son flux de conception
Chakraborty, Avishek · HAL (Le Centre pour la Communication Scientifique Directe) · 2020
Agile heterogeneous embedded computing refers to the consideration of platform architectures as a first class design variable in deploying applications on heterogeneous platforms, which constitute one or more of the following compute engines: FPGA, GPU and CPU. Design flows for agile heterogeneous computing are in the early phases of development. Few state of the art design flows that consider variable platform architectures have the following drawbacks: (1) restricted template-based representations, which cannot express all possible architectural topologies, (2) limited support for concurrent tasks on all three compute engines and (3) design space exploration approaches indirectly consider variable platform architectures, because they are derived from fixed platform design flows, where different platform architectures are iteratively evaluated without closely considering the application's computational needs. This research explores solutions to these three major issues that have yet to be addressed in agile heterogeneous computing design flows. The solutions to these issues are encapsulated into a new design flow called agile heterogeneous computing flow (AhcFlow) that can support both design space exploration and deployment. In order to realise AhcFlow, a new representation to express variable platform architectures called parameterised platform graph (PPG) is conceived, a new intermediate data structure called augmented synchronous dataflow (ArcSDF) is created and a new design space exploration algorithm called agile mapping and scheduling algorithm (AMS) is developed. PPG is a constraint based representation, which unlike template-based representations has higher expressive capabilities to represent the different topologies of agile heterogeneous computing. ArcSDF is a new dataflow based intermediate data structure, which is built on the well-known synchronous dataflow graphs (SDF) to express the architectural decisions together with the application. ArcSDF extends the capabilities of the dataflow paradigm to incorporate computation resource analysis and capital cost analysis. Due to these extra analysis capabilities, ArcSDF is used within design space exploration. The design space exploration algorithm is AMS that considers the variable platform architecture in a fully integrated way together with mapping and scheduling decisions. A prototype of the new design flow (AhcFlow) has been created and shown to be valid both for an exhaustive number of synthetic test cases and for a large real life embedded multi-object visual tracking application. The new analysis capabilities of ArcSDF have been validated through its integration within the design flow prototype. The prototype also consists of a deployment module, which is used to validate the design space exploration predictions with the actual deployment results. The results from the real life tracking application show that design space exploration estimates closely match the deployment results. The new mapping and scheduling algorithm, that also makes architecture topology decisions, has shown to be competitive with published results of applications implemented manually to hand crafted architectures.