Gestion des FPGA et Reconfiguration Dynamique : étude de la virtualisation et de la pré-emption des accélérateurs matériels
Ye Tian · HAL (Le Centre pour la Communication Scientifique Directe) · 2020
Field-Programmable Gate Arrays (FPGAs) have been gaining popularity in heterogeneous architectures due to their high efficiency, reliability, low energy consumption and high performance. Such reconfigurable computing devices come with ever greater quantities of on-chip resources, allowing the development of more complex variety of applications. Therefore, the trend is that technique giants such as Amazon, Microsoft, and Baidu embrace FPGAs to meet their critical computing requirements. In addition, the ability to reprogram these devices in the field is being developed for reliability in application domains such as military, military, aerospace, and nuclear power stations. The management of reconfigurable FPGAs devices constitutes a hot topic in a lot of domains. In such devices, a reconfigurable fabric is generally combined with a processor to guarantee high computing performance with a limited amount of hardware resources. Most of these devices generally feature an operating system (OS) that requires to interact with hardware resources such as accelerators or Intellectual Property (IP) blocks. Software tasks that run on top of the OS may then access hardware resources concurrently and dedicated mechanisms have to be provided to manage resource sharing efficiently. The problem is even bigger if hardware resources are localized in a reconfigurable area that can implement various designs in time. Some IPs may be accessed from tasks with different priorities and preemption mechanisms have to be imagined, as in software. In case of preemption, one issue consists in suspending the IPs and restart them from the very same point of preemption at another time and/or in another position of the reconfigurable part of the FPGA. An hardware accelerator must be able to preserved its internal state and its memory contents so that when it is resumed later, its execution can continue from its preemption point. However, one challenge of partial reconfiguration and context saving/restoring is that it is time consuming, especially as IPs are constantly being reconfigured. In this thesis, we deal with the problem of sharing hardware resources in a reconfigurable device. First, we present simple examples related to hardware resources management and describe how users may benefit from the hardware part to accelerate the access to resources. Second, we proposed new preemption mechanisms on the Reconfigurable System-on-Chip (RSoC) to efficiently and safely manage these reconfigurable resources, which may reduce the reconfiguration time overhead to be compatible with the timing constraints of most embedded applications.