Switch Controlled State Skipping Based Memory Efficient Test Pattern Generator for BIST Application
S. Nagaraju, G. Reddy Hemantha, Shanmugham Balasundaram · 2023
The Test pattern generator (TPGs) is one of the prominent components in any testing environment and decides the overall system performance digital circuits functional verification and emerging steadily in recent years to accommodate highly complex system designs; however significant performance gap still exists in existing TPG modules to meet the design constraints associated to the different system in terms of maximum allowable testing power and fault coverage etc. in this paper novel energy efficient Switch Controlled state transition-based LFSR TPG is introduced to formulate test patterns with maximum length and randomness. Here LFSR generated test vectors using conventional LFSR reseeding model with fixed polynomial configuration is divided and grouped into smaller blocks and used Switch Controlled encoding process to transforming into multiple independent test pattern blocks. The concatenation of these isolated encoder generated blocks improves the randomness in final test vector sequence which also includes transitional and non- transitional values to control the overall switching activity. Moreover, in accordance with the power constrains associated to each binary positions of test vectors some weightages are assigned to control certain bit transitions which can significantly optimize the dynamic power consumption during testing process. Finally Switch controller is used to regulate the state transition with maximal randomness characteristics compared with other LFSR. Here both clock rate and number state in Switch Controlled machine can be dynamically changed to modify the LFSR statistics in accordance with BIST requirements. The proposed work is successfully synthesized in Quartos-II environment tool and based on simulated results for TPG with LFSR the power has been optimized by 3% and the hardware utilization is minimized by 7%