Design and Analysis of 18T Master-Slave Flip-Flop Circuit
G. Rajesh Krishna, Rohit Lorenzo, Sharmila Saha · 2023
A novel master-slave flip-flop is designed using 18 transistors by topological techniques. The proposed flip-flop circuit (PFC) is compared with the existing flip-flops. Key parameters like area, delay, and leakage power are compared and simulated. PFC is simulated using 45nm Complementary Metal Oxide Semiconductor (CMOS) technology. PFC improves average power by 8.75%, 35.4%, and C to Q delay by 15.27%, 55.66% compared to Hybrid Flip-Flop(HFF) and Logic Structure Reduction Flip-Flop (LRFF). Power delay product (PDP) is also improved by 25.45%, and 52.63% compared to HFF and LRFF. Monte Carlo simulations were conducted for 500 samples for access average power and C-to-Q delay. Since there are fewer PMOS transistors in PFC, the total PFC area is 1.52% smaller than that of HFF. PFC is efficient up to 1 GHz of clock frequency.