A 432-CELL SDFL GaAs Gate Array Implementation of a Four-Bit Slice Event Counter with Programmable Threshold and Time Stamp
G. Lee, Todd Steeves, M. Schroeder, R.D. Nelson, Tho Truong Vu, Â. Hanzal, P.C.T. Roberts, M.J. Helix, S.A. Jamison, S.A. Hanka, J. Brown · 1983
A 432-cell GaAs gate array has been built and personalized to implement a four-bit slice count and compare function. Each cell in the array can be programmed to perform one of three logic operations, and ring oscillator results show a nominal gate delay of 250 ps at 3 mW per cell. The array also contains programmable I/o buffers and 64 bits of SRAM. The cells of the array were designed for efficient routing, and a custom CALMA menu was developed to personalize the array. The array personalization consists of 10 macrocells with each utilizing between 17 and 60 cells for a total of 292 cells or 336 equivalent gates.