A 7K GaAs Configurable Cluster Gate Array
R. C. Kezer, Kenneth R. Elliott, Linton G. Salmon, Arthur M. Cappon, E. V. Korpinen, E. R. Walton, S. J. Ross, Chia-Jung Tsen · 1987
A large scale, low power 7056 gate configurable cluster array has been designed, fabricated and tested. The array employed 1 µm gate length MESFETs on 3-in. GaAs wafers using a planar fabrication process. A unique configurable logic cluster utilizing buffered FET logic (BFL) that is internally routable was designed. Internal routability of the cluster allows for the configuration of up to eight-gate high level logic functions, including edge-triggered flip flops, without the use of external routing channels. The use of a cluster design methodology reduces parasitic loading effects due to interconnects necessary to generate many logic functions, thereby increasing the speed of a personalized system. The logic gate design employs the use of narrow, 3 µm, -0.5 V threshold devices. The pullup and pulldown devices have been sized equally to obtain large dc noise margins and decreased temperature sensitivity for operation over the military temperature range of -55°C to 125°C. The design of the basic BFL gate and the cluster allows for the use of a new complex gating technique whereby input transistors can supply either inverting or noninverting inputs. Several complex gates have been developed as part of the macrocell library for use in this array. Included are a one gate delay exclusive OR (EXOR) gate which dissipates less power than conventional exclusive or gate designs, and an edge-triggered D flip-flop with a clock to data delay of four-gate delays rather than the five-gate delays of traditional designs.