Circuit Implementation of Modular Adders in Custom CMOS VLSI and FPGA
П. Н. Бибило, Н. А. Кириенко · Russian Microelectronics · 2023
Abstract— Modular arithmetic is often used to create high-speed computing systems based on both custom digital VLSI circuits and field-programmable gate arrays (FPGAs). The problems of hardware implementation of neural networks based on modular arithmetic calculations are relevant today. In this study, the problem of implementing modular adders in the library for designing custom CMOS VLSI systems and FPGAs is considered. Systems of both fully and incompletely defined (partial) Boolean functions, as well as algorithmic descriptions in the VHDL language, are used as the initial descriptions of modular adders. Logical optimization preceding logical synthesis is carried out in the class of disjunctive normal forms, Reed–Muller polynomial representations, and representations of Boolean function systems by binary decision diagrams. Nine experiments are carried out on the efficiency of applying logic optimization in the circuit implementation of modular adders in the library for designing custom CMOS VLSI circuits and FPGAs. The obtained circuits of modular adders for CMOS VLSI systems are estimated by area (total number of transistors), delay, and power consumption; and for FPGAs, by the number of programmable logic elements and power consumption. The experimental results show that the use of partial function models and preliminary logical optimization based on binary decision diagrams makes it possible to obtain modular adders characterized by lower delay values. Algorithmic VHDL models make it possible to obtain CMOS modular adder circuits with a smaller area and lower power consumption.