Hybrid SC-SCL Decoder for Polar Codes with Low Latency
Shunfu Zhong, Kai Niu, Chao Dong, Hongji Cui · 2023
This paper describes the hardware implementation of successive cancellation (SC) and CRC-aided successive cancellation list (CA-SCL) decoders based on polar codes, and demonstrates hybrid decoding of the two algorithms. This decoder mainly includes memory, processing elements (PE), path metric (PM) and partial sum (PSUM), and acceleration unit. The independent SC decoder and the SCL decoder are hybrid by sharing the channel-side likelihood ratio (LLR) memory resources. The PE unit employs a three-stage pipeline for LLR computation, while the acceleration unit utilizes look-ahead carry decoding. This significantly reduces decoding time and improves decoding performance. The hardware implementation and testing are conducted on Xilinx FPGA boards and compared with state-of-the-art (SOTA) methods.