HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
Kingshuk Majumder, Uday Kumar Reddy Bondhugula · 2023
The emergence of machine learning, image and audio processing on edge devices has motivated research towards power-efficient custom hardware accelerators. Though FPGAs are an ideal target for custom accelerators, the difficulty of hardware design and the lack of vendor agnostic, standardized hardware compilation infrastructure has hindered their adoption.