NOEL-V FT and GRSCRUB IP: Fault Tolerance Characterization of a Complex System-on-Chip on Xilinx Kintex UltraScale FPGA
Ádria Barros de Oliveira, Lucas Antunes Tambara, Olle Lexell, Fabio Malatesta, Nils-Johan Wessman, Johan Klockars, Arvid Björkengren, Jan Andersson · 2022
This work presents the SEE fault tolerance characterization of the NOEL-V FT RISC-V processor IP core combined with the GRSCRUB FPGA supervisor protection on a Xilinx Kintex UltraScale FPGA. Additionally, a distributed TMR synthesis strategy is applied to enhance the resilience of the system against SEE. Results from a proton beam irradiation show the efficiency of the NOEL-V fault tolerance features in correcting single errors and preventing error accumulation, the GRSCRUB’s advanced capability of error detection and correction, and the masking effects of the distributed TMR method.