Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System
Zengshi Wang, Chao Fu, Jun Shu Han · 2023
An increasing interest in accelerators occurs in recent years due to the demand for high performance and power efficient computing. However, the potential negative effects resulting from the competition for hardware resources between accelerators and CPUs have not been well investigated. In this paper we introduce DPCP, a scheme that combines the data prefetching and static data partitioning to reduce the data interference in shared cache and improve the performance of both accelerators and CPUs. Our research demonstrates that the DPCP scheme delivers an average 11% improvement in IPC (Instructions Per Cycle) for non-accelerated tasks, surpassing the gains of data prefetching alone by 10% and cache partitioning alone by 3%, and achieves a 13% increase in accelerator speedup.