Efficient Layout Pattern Matching Based on Local Information
Wuxin Ge, Chao Wang · 2023
Pattern matching is a widely used technique in IC physical verification. As the circuit feature size shrinks and the complexity of the pattern grows, the searching and matching process for layout pattern matching becomes increasingly time-consuming. To address this issue, a more efficient layout pattern matching method that takes into account the specific characteristics of the layout is developed. Our method first partitions and groups layout patterns, and then utilizes an efficient memory model to store rectangular data. Secondly, features of layout patterns are considered, and local information about the pattern is used for filtering and matching. Furthermore, multi-threading is employed to further improve the algorithm’s efficiency. Experimental results demonstrate that the proposed method achieves a speedup ranging from 2.0× to 3.8× when compared to the most advanced pattern matching algorithm and even higher acceleration when compared to other approaches while maintaining a query success rate of 100%. These results highlight the effectiveness and superiority of this method for layout pattern matching in the physical verification of integrated circuits.