Design and implementation of low power D flip flop for embedded application
R. A. Burange, G. H. Agrawal, Kartik Ingole · AIP conference proceedings · 2024
The power consumption of digital systems might be drastically cut down if the power consumption of flipflops (FFs) was optimized.We suggest a true single-phase-clocked (TSPC) retention FF as a means of power conservation.The proposed TSPC FF takes into account the inputs to determine whether and when precharging are necessary.Float node analysis and semiconductor level improvements are also done to guarantee the FF's exceptional energy efficiency without considerably expanding its size.The suggested FF consumes 30.37% less power than a standard transmission-gate flip-flop under the same conditions (10% data activity and 0.95 V supply voltage) (TGFF).As data activity reaches 0%, the proportion of decrease increases to 99.53 percent.