Current state and next generation of a systolic array SoC in space
C. Papadas, Tilemachos Tsiapras, Richard Wiest, Ioannis Katelouzos, Grigorios Papoulis, David Steenari, Kostas Makris, T. Helfers, Laurent Hili · 2023
The field of space applications has always been one of the most demanding and the challenges range from low power consumption to high performance data processing capabilities and from long component lifetime to remote control and flexibility. Engineers have to exploit each attribute the hardware provides and every particular requirement has to be coupled with an adequate design choice. The use of systolic arrays in a processing units brings to the arsenal of designers the possibility to have a very flexible and easily programmable solution, capable of performing parallelization of the most advanced and complex algorithms. After a brief description of the state-of-the-art HPDP chip and its multichip processing node, we will describe the next version of the device currently under design.