A heterogeneous simulation platform with LEON5 and IEEE standard real-time operating system
Hiroki Hihara, Kuniyuki Omagari, Kazuyo Mizushima, Daichi Imazato, Tadateru Takahashi, Takeshi Takashima, Mitsuhisa Yamaji, Kyosuke Kuze · 2023
We developed a heterogeneous simulation platform with a LEON5 processor and Dynamically Reconfigurable Processors (DRPs) for DESTINY+ science and technology demonstration mission. A LEON5 processor is implemented on a Field Programmable Gate Array (FPGA), and IEEE Standard for a Real-Time Operating System (RTOS) for Small-Scale Embedded Systems is adopted on the processor. SpaceWire, SpaceFibre, and PCI Express interfaces are integrated with a router to enhance its simulation capability for the simulation of a whole satellite system. In addition to artificial intelligence processing capabilities of DRPs, interfaces for general purpose graphics processing units (GPGPUs) and vector processing units of super computers are also incorporated. We report the development result of the platform in this paper.