Design and analysis of CMOS based multiplier using LFSR
Harika Sadhineni, S. Josaph, N. Vaishnavi · AIP conference proceedings · 2024
In this paper, we designed the CMOS based multiplier using LFSR for high-speed operation.Basically, the memory cells, multidimensional memory circuits and memory frameworks are referenced with various sub-chips.The main intent behind using Linear Feedback Shift Register (LFSR) Controller is to provide full speed operations.The proposed architecture plans fullspeed activity of some non-straight calculations that are winding up increasingly more significant in present day memory testing, conclusion.The combinational logic and scan logic provides a solution to the system in a specified manner.Compared to existed design, the proposed system gives effective results.